Despite advances in semiconductor process technology, it is well known that integrated circuit memories can be manufactured with errors. Just a single bit error can render a memory unusable, and because of this manufacturers have implemented various techniques to repair memories in which memory cells can be identified as being faulty. For example, memories can include redundant rows or columns of memory cells. These redundant circuits are not used when the memory's non-redundant memory cells contain no manufacturing errors. However, should a memory cell be determined to be faulty, a redundant memory component can be substituted for one of the non-redundant memory components such that the overall memory component (although including the faulty memory cell) can still be used. For example, a redundant row of memory cells can instead be addressed in a row redundancy scheme where a non-redundant row is determined to include a faulty memory cell.
In order to speed up the diagnosis of errors in memory cells, integrated circuits are often provided with built-in self-testing (BIST) circuitry. The BIST circuitry can be used to test parts of the circuit. For example, an integrated circuit which has BIST circuitry can be tested by automated test equipment (ATE). As the overall yield of a system-on-chip, for example, is dominated by the yield of the included memory cores, the use of some type of redundancy scheme for the memory cores can assist in improving device yield to almost 99%.
Typically, during testing at production level, the memory is also tested. If one or more locations of the memory are not functional, the redundant circuits can be invoked inside the memory. After repair, the memory is tested again for complete functionality. Where all of the memory locations are properly functioning, the redundancy elements are not typically tested at all.
However, even where the memory is initially determined to be fully functional in the first run, it may be of some use to also test the redundancy elements. For example, it can be useful in providing in-field repair capability to the memory should the memory subsequently develop a failure. In such a case wherein the fault arises during the working life of the memory, the memory is capable of being repaired by invoking the redundancy (provided there is no fault in the redundant circuitry).
Several processes have been proposed in order to support an “in field” testing of the memory. All of the approaches mentioned are used for testing the memory at the time of production. If the memory has a failing location, it is discarded. If all the address space of the memory is functional, then the memory is tested again for the repair elements.
In a first approach the entire memory is first checked (this is referred to as a CEM or check entire memory operation) with the redundancy elements disabled, followed by a further test where for each redundancy address on the redundancy pin of the memory, the entire memory is checked with the redundancy enabled.
In such an approach, while the comparator logic has been tested sufficiently, testing the regular array faults have not created proper stress patterns including a row fast pattern, that is a part of standard built-in self-test (BIST) algorithm. Hence, the failing row and the row adjacent to it are not stressed to the maximum. Although this is a fairly simple built-in self-test algorithm, it requires a prohibitive amount of time in order to carry it out.
To attempt to overcome the speed penalty of the above, such systems alter the second testing step, the step prior to repair, by setting the redundancy address pin at 0. In other words the redundancy row is set adjacent to actual row 0 and testing the entire memory with the redundancy is enabled. However, this approach not only fails to create proper stress patterns but also fails to check for decoder faults.
Furthermore, to further speed up the testing process the redundancy address pin can be set to 0 and only the locations 0 and 1 are checked. Although this is the fastest of the three test processes described, this has the additional problem of a higher probability of missing decoder faults.
A need exists in the art to address the foregoing testing problems.